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LTC1863L/LTC1867L Micropower, 3V, 12-/16-Bit, 8-Channel 175ksps ADCs
FEATURES

DESCRIPTIO

Sample Rate: 175ksps 16-Bit No Missing Codes and 3LSB Max INL 8-Channel Multiplexer with: Single Ended or Differential Inputs and Unipolar or Bipolar Conversion Modes SPI/MICROWIRETM Serial I/O 2.7V Guaranteed Supply Voltage Pin Compatible with LTC1863/LTC1867 True Differential Inputs On-Chip or External Reference Low Power: 750A at 175ksps, 300A at 50ksps Sleep Mode Automatic Nap Mode Between Conversions 16-Pin Narrow SSOP Package
The LTC(R)1863L/LTC1867L are pin compatible, 8-channel 12-/16-bit A/D converters with serial I/O and an internal reference. The 8-channel input multiplexer can be configured for either single-ended or differential inputs and unipolar or bipolar conversions (or combinations thereof). The ADCs convert 0V to 2.5V unipolar inputs or 1.25V bipolar inputs. The ADCs typically draw only 750A from a single 2.7V supply. The automatic nap and sleep modes benefit power sensitive applications. The LTC1867L's DC performance is outstanding with a 3LSB INL specification and 16-bit no missing codes over temperature. Housed in a compact, narrow 16-pin SSOP package, the LTC1863L/LTC1867L can be used in space-sensitive as well as low power applications.
, LTC and LT are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
APPLICATIO S

Industrial Process Control High Speed Data Acquisition Battery Operated Systems Multiplexed Data Acquisition Systems Imaging Systems
BLOCK DIAGRA
CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7/COM 1 2 3 4 5 6 7 8 ANALOG INPUT MUX
LTC1863L/LTC1867L
Integral Nonlinearity vs Output Code (LTC1867L)
16 15 14 VDD GND SDI SDO SCK CS/CONV VREF
INL (LSB)
2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5
VDD = 2.7V fSAMPLE = 175ksps
+ -
12-/16-BIT 175ksps ADC
SERIAL PORT
13 12 11 10
INTERNAL 1.25V REF
9
1863L7L BD
REFCOMP
-2.0
0
U
16384 32768 OUTPUT CODE
1863L7L G01
W
U
49152
65536
1863L7Lf
1
LTC1863L/LTC1867L
ABSOLUTE
(Notes 1, 2)
AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW CH0 1 CH1 2 CH2 3 CH3 4 CH4 5 CH5 6 CH6 7 CH7/COM 8 16 VDD 15 GND 14 SDI 13 SDO 12 SCK 11 CS/CONV 10 VREF 9 REFCOMP
Supply Voltage (VDD) ................................... -0.3V to 6V Analog Input Voltage CH0-CH7/COM (Note 3) .......... - 0.3V to (VDD + 0.3V) VREF, REFCOMP (Note 4)......... - 0.3V to (VDD + 0.3V) Digital Input Voltage (SDI, SCK, CS/CONV) (Note 4) .................................................- 0.3V to 10V Digital Output Voltage (SDO) ....... - 0.3V to (VDD + 0.3V) Power Dissipation .............................................. 500mW Operating Temperature Range LTC1863LC/LTC1867LC/LTC1867LAC .... 0C to 70C LTC1863LI/LTC1867LI/LTC1867LAI .. - 40C to 85C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C
ORDER PART NUMBER LTC1863LCGN LTC1863LIGN LTC1867LCGN LTC1867LIGN LTC1867LACGN LTC1867LAIGN GN PART MARKING 1863L 1863LI 1867L*
GN PACKAGE 16-LEAD NARROW PLASTIC SSOP TJMAX = 110C, JA = 95C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
CO VERTER CHARACTERISTICS
PARAMETER Resolution No Missing Codes Integral Linearity Error Differential Linearity Error Transition Noise Offset Error Offset Error Match Offset Error Drift Gain Error Gain Error Match Gain Error Tempco Power Supply Sensitivity Unipolar Bipolar Unipolar Bipolar Internal Reference External Reference VDD = 2.7V - 3.6V Unipolar (Note 8) Bipolar Unipolar Bipolar

The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VDD = 2.7V, external VREF = 1.25V (Notes 5, 6)
CONDITIONS

MIN 12 12
LTC1863L TYP MAX
MIN 16 15
LTC1867L TYP MAX
MIN 16 16
LTC1867LA TYP MAX
UNITS Bits Bits
Unipolar (Note 7) Bipolar

1 1 1 0.1 3 4 1 1 0.5 6 6 1 1 20 3 1 20 3 3 0.5 -2 1.6
4 4 -1 1.6 32 64 4 4 0.5 96 96 4 4 20 3 3
3 3
LSBRMS 32 64 3 3 64 64 3 3 LSB LSB LSB LSB ppm/C LSB LSB LSB LSB ppm/C ppm/C LSB
DY A IC ACCURACY
SYMBOL SNR S/(N+D) PARAMETER Signal-to-Noise Ratio Signal-to-(Noise + Distortion) Ratio
VDD = 3V, external VREF = 1.25V (Note 5)
CONDITIONS 1kHz Input Signal 1kHz Input Signal MIN LTC1863L TYP MAX 73.2 73.1 LTC1867L/LTC1867LA MIN TYP MAX 83.3 82.6 UNITS dB dB
1863L7Lf
2
U
LSB LSB LSB
W
U
U
WW
W
WU
U
LTC1863L/LTC1867L
DY A IC ACCURACY
SYMBOL THD PARAMETER Total Harmonic Distortion Peak Harmonic or Spurious Noise Channel-to-Channel Isolation Full Power Bandwidth
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5)
SYMBOL PARAMETER Analog Input Range CIN tACQ Analog Input Capacitance for CH0 to CH7/COM Sample-and-Hold Acquisition Time Input Leakage Current On Channels, CHX = 0V or VDD CONDITIONS Unipolar Mode (Note 9) Bipolar Mode Between Conversions (Sample Mode) During Conversions (Hold Mode)

A ALOG I PUT
I TER AL REFERE CE CHARACTERISTICS
PARAMETER VREF Output Voltage VREF Output Tempco VREF Line Regulation VREF Output Resistance REFCOMP Output Voltage CONDITIONS IOUT = 0 IOUT = 0 2.7V VDD 3.6V IOUT 0.1mA IOUT = 0
DIGITAL I PUTS A D DIGITAL OUTPUTS
SYMBOL VIH VIL IIN CIN VOH VOL ISOURCE ISINK PARAMETER High Level Input Voltage Low Level Input Voltage Digital Input Current Digital Input Capacitance High Level Output Voltage (SDO) Low Level Output Voltage (SDO) Output Source Current Output Sink Current Hi-Z Output Leakage Hi-Z Output Capacitance Data Format CONDITIONS VDD = 3.6V VDD = 2.7V VIN = 0V to VDD
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5)
LTC1863L/LTC1867L/LTC1867LA MIN TYP MAX

U
U
U
U
WU
U
VDD = 3V, external VREF = 1.25V (Note 5)
CONDITIONS 1kHz Input Signal, Up to 5th Harmonic 1kHz Input Signal 100kHz Input Signal -3dB Point MIN LTC1863L TYP MAX -92.3 -94.5 -100 1.25 LTC1867L/LTC1867LA MIN TYP MAX - 91 - 92.8 -112 1.25 UNITS dB dB dB MHz
U
LTC1863L/LTC1867L/LTC1867LA MIN TYP MAX 0 to 2.5 1.25 32 4 2.01 1.68 1
UNITS V V pF pF s A
U
(Note 5)
LTC1863L/LTC1867L/LTC1867LA MIN TYP MAX 1.235 1.25 20 0.3 3 2.5 1.265 UNITS V ppm/C mV/V k V
UNITS V V A pF V V
1.9 0.45 10 2 2.68 2.65 0.05 0.15 -9.7 6 0.4
VDD = 2.7V, IO = -10A VDD = 2.7V, IO = -200A VDD = 2.7V, IO = 160A VDD = 2.7V, IO = 1.6mA SDO = 0V SDO = VDD CS/CONV = High, SDO = 0V or VDD CS/CONV = High (Note 10) Unipolar Bipolar

2.3
V V mA mA

10 15 Straight Binary Two's Complement
A pF
1863L7Lf
3
LTC1863L/LTC1867L
POWER REQUIRE E TS
SYMBOL VDD IDD PARAMETER Supply Voltage Supply Current
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5)
CONDITIONS (Note 9) fSAMPLE = 175ksps, Internal REF NAP Mode SLEEP Mode fSAMPLE = 175ksps

PDISS
Power Dissipation
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5)
SYMBOL fSAMPLE tCONV tACQ fSCK t1 t2 t3 t4 t5 t6 t7 t8 PARAMETER Maximum Sampling Frequency Conversion Time Acquisition Time SCK Frequency CS/CONV High Time SDO Valid After SCK SDO Valid Hold Time After SCK SDO Valid After CS/CONV SDI Setup Time Before SCK SDI Hold Time After SCK SLEEP Mode Wake-Up Time Bus Relinquish Time After CS/CONV CREFCOMP = 10F, CVREF = 2.2F CL = 25pF
TI I G CHARACTERISTICS
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to GND (unless otherwise noted). Note 3: When these pin voltages are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA without latchup. Note 4: When these pin voltages are taken below GND, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND without latchup. These pins are not clamped to VDD. Note 5: VDD = 2.7V, fSAMPLE = 175ksps and fSCK = 20MHz at 25C, t r = t f = 5ns and VIN - = 1.25V for bipolar mode unless otherwise specified. Note 6: Linearity, offset and gain error specifications apply for both unipolar and bipolar modes. The INL and DNL are tested in bipolar mode. Note 7: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band.
4
UW
LTC1863L/LTC1867L/LTC1867LA MIN TYP MAX 2.7 0.75 170 0.2 2 3.6 1 3 2.7
UNITS V mA A A mW
UW
CONDITIONS

LTC1863L/LTC1867L/LTC1867LA MIN TYP MAX 175 3.2 2.01 40 5 15 15 1.68 20 100 22 17 20 -6 6 80 30 50 40 47 3.7
UNITS kHz s s MHz ns ns ns ns ns ns ms ns
Short CS/CONV Pulse Mode CL = 25pF (Note 11) CL = 25pF CL = 25pF

Note 8: Unipolar offset is the offset voltage measured from +1/2LSB when the output code flickers between 0000 0000 0000 0000 and 0000 0000 0000 0001 for LTC1867L and between 0000 0000 0000 and 0000 0000 0001 for LTC1863L. Bipolar offset is the offset voltage measured from -1/2LSB when output code flickers between 0000 0000 0000 0000 and 1111 1111 1111 1111 for LTC1867L, and between 0000 0000 0000 and 1111 1111 1111 for LTC1863L. Note 9: Recommended operating conditions. The input range of 1.25V for bipolar mode is measured with respect to VIN - = 1.25V. For unipolar mode, common mode input range is 0V to VDD for the positive input and 0V to 1.5V for the negative input. For bipolar mode, common mode input range is 0V to VDD for both positive and negative inputs. Note 10: Guaranteed by design, not subject to test. Note 11: t2 of 47ns maximum allows fSCK up to 10MHz for rising capture with 50% duty cycle and fSCK up to 20MHz for falling capture (with 3ns setup time for the receiving logic).
1863L7Lf
LTC1863L/LTC1867L TYPICAL PERFOR A CE CHARACTERISTICS
Integral Nonlinearity vs Output Code
2.0 1.5 1.0 VDD = 2.7V fSAMPLE = 175ksps 2.0 1.5 1.0
DNL (LSB)
INL (LSB)
0.5 0 -0.5 -1.0 -1.5 -2.0 0 16384 32768 OUTPUT CODE
1863L7L G01
0.5 0 -0.5 -1.0 -1.5
AMPLITUDE (dB)
49152
4096 Points FFT Plot (VDD = 3V, REFCOMP = Ext 3V)
0 -20 -40 -60 -80 -100 -120 -140 0 21.875 65.625 FREQUENCY (kHz) 43.75 87.5
-60
RESULTING AMPLITUDE ON SELECTED CHANNEL (dB)
AMPLITUDE (dB)
fSAMPLE = 175ksps fIN = 1kHz SNR = 84.7dB SINAD = 83.5dB THD = 90dB
-90 -100 -110 -120 -130 ADJACENT PAIR NONADJACENT PAIR
AMPLITUDE (dB)
Total Harmonic Distortion vs Input Frequency
-100 -90 -80 AMPLITUDE (dB) SFDR -70 THD -60 -50 -40 VDD = 3V -30 INTERNAL REF fSAMPLE = 175ksps -20 1 10 INPUT FREQUENCY (kHz)
POWER SUPPLY FEEDTHROUGH (dB)
SUPPLY CURRENT (A)
UW
1863L7L G04
1863L7L G06
(LTC1867L) 4096 Points FFT Plot (VDD = 2.7V, Internal REF)
0 -20 -40 -60 -80 -100 -120 -140 fSAMPLE = 175ksps fIN = 1kHz SNR = 82.9dB SINAD = 81.4dB THD = 86.8dB
Differential Nonlinearity vs Output Code
VDD = 2.7V fSAMPLE = 175ksps
65536
-2.0
0
16384
32768 OUTPUT CODE
49152
65536
0
21.875
43.75 65.625 FREQUENCY (kHz)
87.5
1863L7L G02
1863L7L G03
Crosstalk vs Input Frequency
-70 -80 VDD = 3V fSAMPLE = 175ksps
100 90
Signal-to-(Noise + Distortion) Ratio vs Input Frequency
SNR 80 70 SINAD 60 50 40 VDD = 3V 30 INTERNAL REF fSAMPLE = 175ksps 20 1 10 INPUT FREQUENCY (kHz)
-140 0.1 10 100 1000 1 ACTIVE CHANNEL INPUT FREQUENCY (kHz)
1863L7L G05
100
1863L7L G06
Power Supply Feedthrough vs Ripple Frequency
VDD = 3V -30 fSAMPLE = 175ksps VRIPPLE = 10mVP-P -40 -50 -60 -70 -80 -90 -100
100
Supply Current vs fSAMPLE (LTC1863L/LTC1867L)
800 700 600 500 400 300 200 100 VDD = 2.7V
-20
1
10 100 RIPPLE FREQUENCY (kHz)
1000
1863L7L G08
1
10 100 fSAMPLE (ksps)
1000
1863L7L G09
1863L7Lf
5
LTC1863L/LTC1867L TYPICAL PERFOR A CE CHARACTERISTICS
Supply Current vs Supply Voltage
1200 1100 fSAMPLE = 175ksps
1500
SUPPLY CURRENT (A)
SUPPLY CURRENT (A)
1000 900 800 700 600
1000
3.3VDD 3VDD
COUNTS
2.7
3 3.3 SUPPLY VOLTAGE (V)
REFCOMP vs Load Current
2.510 2.505 2.500 VDD = 2.7V
10
UNIPOLAR OFFSET (LSB)
5 BIPOLAR MODE 0
UNIPOLAR OFFSET (LSB)
REFCOMP (V)
2.495 2.490 2.485 2.480 2.475 0 0.5 1.5 LOAD CURRENT (mA) 1 2
1863L7L G13
Integral Nonlinearity vs Output Code (LTC1863L)
1.00 0.75 0.50 1.00 0.75 0.50
0 -0.25 -0.50 -0.75 -1.00 0 512 1024 1536 2048 2560 3072 3584 4096 CODE
1863L7L G16
DNL (LSB)
INL (LSB)
0.25
6
UW
1963L7L G10
(LTC1863L/LTC1867L) Histogram for 4096 Conversions (LTC1867L)
1200 1044 1000 895 830 800 600 465 400 200 170 7 58 23 9 1 333 261 VDD = 2.7V INTERNAL REF
Supply Current vs Temperature
fSAMPLE = 175ksps INTERNAL REF
1250
3.6VDD
750
2.7VDD
3.6
500 -50
0
-25 0 25 50 TEMPERATURE (C) 75 100
20 21 22 23 24 25 26 27 28 29 30 31 CODE
1863L7L G12
1863L7L G11
Offset Drift (LTC1867L) vs Temperature
15
VDD = 2.7V fSAMPLE = 175ksps EXT VREF = 1.25V UNIPOLAR MODE
Gain Error Drift (LTC1867L) vs Temperature
VDD = 2.7V fSAMPLE = 175ksps EXT VREF = 1.25V UNIPOLAR/BIPOLAR
10 5 0 -5 -10
-5
-10 -50
-25
0 25 50 TEMPERATURE (C)
75
100
-15 -50
-25
0 25 50 TEMPERATURE (C)
75
100
1863L7L G14
1863L7L G15
Differential Nonlinearity vs Output Code (LTC1863L)
0.25 0 -0.25 -0.50 -0.75 -1.00 0 512 1024 1536 2048 2560 3072 3584 4096 CODE
1863L7L G17
1863L7Lf
LTC1863L/LTC1867L
PI FU CTIO S
CHO-CH7/COM (Pins 1-8): Analog Input Pins. Analog inputs must be free of noise with respect to GND. CH7/ COM can be either a separate channel or the common minus input for the other channels. Unused channels should be tied to ground. REFCOMP (Pin 9): Reference Buffer Output Pin. Bypass to GND with 10F tantalum capacitor in parallel with 0.1F ceramic capacitor (2.5V Nominal). To overdrive REFCOMP, tie VREF to GND. VREF (Pin 10): 1.25V Reference Output. This pin can also be used as an external reference buffer input for improved accuracy and drift. Bypass to GND with 2.2F tantalum capacitor in parallel with 0.1F ceramic capacitor. CS/CONV (Pin 11): This input provides the dual function of initiating conversions on the ADC and also frames the serial data transfer. SCK (Pin 12): Shift Clock. This clock synchronizes the serial data transfer. SDO (Pin 13): Digital Data Output. The A/D conversion result is shifted out of this output. Straight binary format for unipolar mode and two's complement format for bipolar mode. SDI (Pin 14): Digital Data Input Pin. The A/D configuration word is shifted into this input. GND (Pin 15): Analog and Digital GND. VDD (Pin 16): Analog and Digital Power Supply. Bypass to GND with 10F tantalum capacitor in parallel with 0.1F ceramic capacitor.
TYPICAL CO
ECTIO
DIAGRA
+ -
1.25V DIFFERENTIAL INPUTS
CH0 CH1 CH2
2.5V SINGLE-ENDED INPUT
LTC1863L/ CH3 SDO LTC1867L
+
CH4 CH5 CH6 CH7/COM
TEST CIRCUITS
Load Circuits for Access Timing
2.7V 3k SDO 3k CL SDO CL SDO 3k CL SDO CL
(A) Hi-Z TO VOH AND VOL TO VOH
(B) Hi-Z TO VOL AND VOH TO VOL
1863L7L TC01
U U
U
UU
U
U
U
VDD GND SDI
2.7V TO 3.6V 10F
SCK CS/CONV VREF REFCOMP
DIGITAL I/O
1.25V 2.2F 2.5V 10F
1863L7L TCD
Load Circuits for Output Float Delay
2.7V 3k
(A) VOH TO Hi-Z
(B) VOL TO Hi-Z
1863L7L TC02
1863L7Lf
7
LTC1863L/LTC1867L
TI I G DIAGRA S
t1 (For Short Pulse Mode)
t1 CS/CONV 50% 50%
t4 (SDO Valid After CS/CONV)
t4 CS/CONV SCK
0.45V
SDO
Hi-Z
t7 (SLEEP Mode Wake-Up Time)
t7 SCK 50% SLEEP BIT (SLP = 0) READ-IN CS/CONV 50% SDO CS/CONV
APPLICATIO S I FOR ATIO
Overview
The LTC1863L/LTC1867L are complete, low power, multiplexed ADCs. They consist of a 12-/16-bit, 175ksps capacitive successive approximation A/D converter, a precision internal reference, a configurable 8-channel analog input multiplexer (MUX) and a serial port for data transfer. Conversions are started by a rising edge on the CS/CONV input. Once a conversion cycle has begun, it cannot be restarted. Between conversions, the ADCs receive an input word for channel selection and output the conversion result, and the analog input is acquired in preparation for the next conversion. In the acquire phase, a minimum time of 2.01s will provide enough time for the sample-andhold capacitors to acquire the analog signal.
8
U
W
W
UU
UW
t2 (SDO Valid After SCK), t 3 (SDO Valid Hold Time After SCK)
t2 SCK 0.45V t3 1.9V 0.45V
SDO
t 5 (SDI Setup Time Before SCK), t6 (SDI Hold Time After SCK)
t5 1.9V t6
1.9V 0.45V
SDI
1.9V 0.45V
1.9V 0.45V
t 8 (BUS Relinquish Time)
t8 1.9V
90% 10%
Hi-Z
1863L7L TD
During the conversion, the internal differential 16-bit capacitive DAC output is sequenced by the SAR from the most significant bit (MSB) to the least significant bit (LSB). The input is sucessively compared with the binary weighted charges supplied by the differential capacitive DAC. Bit decisions are made by a low power, differential comparator that rejects common mode noise. At the end of a conversion, the DAC output balances the analog input. The SAR content (a 12-/16-bit data word) that represents the analog input is loaded into the 12-/16-bit output latches.
1863L7Lf
LTC1863L/LTC1867L
APPLICATIO S I FOR ATIO
Analog Input Multiplexer
The analog input multiplexer is controlled by a 7-bit input data word. The input data word is defined as follows: SD OS S1 S0 COM UNI SLP SD = SINGLE/DIFFERENTIAL BIT OS = ODD/SIGN BIT S1 = ADDRESS SELECT BIT 1 S0 = ADDRESS SELECT BIT 0 COM = CH7/COM CONFIGURATION BIT UNI = UNIPOLAR/BIPOLAR BIT SLP = SLEEP MODE BIT
Examples of Multiplexer Options
4 Differential 8 Single-Ended
+ (-) - (+) { + (-) - (+) { + (-) - (+) { + (-) - (+) {
CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7/COM
+ + + + + + + +
CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7/COM GND (-)
7 Single-Ended to CH7/COM
Combinations of Differential and Single-Ended
+ + + + + + +
CH0 CH1 CH2 CH3 CH4 CH5 CH6
+ -{ - +{ + + + +
CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7/COM GND (-)
1863L7L AI01
CH7/COM (-)
U U
Changing the MUX Assignment "On the Fly"
1st Conversion 2nd Conversion
W W
UU UU
+ -{ + -{
CH2 CH3 CH4 CH5 CH7/COM (UNUSED)
- + + +
{ {
CH2 CH3 CH4 CH5 CH7/COM (-)
1863L7L AI02
Tables 1 and 2 show the configurations when COM = 0, and COM = 1.
Table 1. Channel Configuration (When COM = 0, CH7/COM Pin Is Used as CH7)
SD 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 OS 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 S1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 COM 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Channel Configuration "+" "-" CH0 CH2 CH4 CH6 CH1 CH3 CH5 CH7 CH0 CH2 CH4 CH6 CH1 CH3 CH5 CH7 CH1 CH3 CH5 CH7 CH0 CH2 CH4 CH6 GND GND GND GND GND GND GND GND
Table 2. Channel Configuration (When COM = 1, CH7/COM Pin Is Used as COMMON)
SD 1 1 1 1 1 1 1 OS 0 0 0 0 1 1 1 S1 0 0 1 1 0 0 1 S0 0 1 0 1 0 1 0 COM 1 1 1 1 1 1 1 Channel Configuration "+" "-" CH0 CH2 CH4 CH6 CH1 CH3 CH5 CH7/COM CH7/COM CH7/COM CH7/COM CH7/COM CH7/COM CH7/COM
1863L7Lf
9
LTC1863L/LTC1867L
APPLICATIO S I FOR ATIO
Driving the Analog Inputs
The analog inputs of the LTC1863L/LTC1867L are easy to drive. Each of the analog inputs can be used as a singleended input relative to the GND pin (CH0-GND, CH1-GND, etc) or in pairs (CH0 and CH1, CH2 and CH3, CH4 and CH5, CH6 and CH7) for differential inputs. In addition, CH7 can act as a COM pin for both single-ended and differential modes if the COM bit in the input word is high. Regardless of the MUX configuration, the "+" and "-" inputs are sampled at the same instant. Any unwanted signal that is common mode to both inputs will be reduced by the common mode rejection of the sample-and-hold circuit. The inputs draw only one small current spike while charging the sample-and-hold capacitors during the acquire mode. In conversion mode, the analog inputs draw only a small leakage current. If the source impedance of the driving circuit is low then the LTC1863L/LTC1867L inputs can be driven directly. More acquisition time should be allowed for a higher impedance source. The following list is a summary of the op amps that are suitable for driving the LTC1863L/LTC1867L. More detailed information is available in the Linear Technology data books or Linear Technology website. LT(R)1468: 90MHz, 22V/s 16-bit accurate amplifier LT1469: Dual LT1468 LT1490A/LT1491A: Dual/quad micropower amplifiers, 50A/amplifier max, 500V offset, common mode range extends 44V above V- independent of V+, 3V, 5V and 15V supplies. LT1568: Very low noise, active RC filter building block, cutoff frequency up to 10MHz, 2.7V to 5V supplies.
ANALOG INPUT
50 CH0 2000pF GND LTC1863L/ LTC1867L
REFCOMP 10F
1863L7L F01a
Figure 1a. Optional RC Input Filtering for Single-Ended Input
10
U
LT1638/LT1639: Dual/quad 1.2MHz, 0.4V/s amplifiers, 230A per amplifier, 3V, 5V and 15V supplies. LT1881/LT1882: Dual and quad, 200pA bias current, railto-rail output op amps, up to 15V supplies. LTC1992-2: Gain of 2 fully differential input/output amplifier/driver, 2.5mV offset, CLOAD stable, 2.7V to 5V supplies. LT1995: 30MHz, 1000V/s gain selectable amplifier, pin configurable as a difference amplifier, inverting and noninverting amplifier, 2.5V to 15V supplies. LTC6912: Dual programmable gain amplifiers with SPI serial interface, 2mV offset, 2.7V to 5V supplies. LTC6915: Zero drift, instrumentation amplifier with SPI programmable gain, 125dB CMRR, 0.1% gain accuracy, 10V offset. Input Filtering The noise and the distortion of the input amplifier and other circuitry must be considered since they will add to the LTC1863L/LTC1867L noise and distortion. Noisy input circuitry should be filtered prior to the analog inputs to minimize noise. A simple 1-pole RC filter is sufficient for many applications. For instance, Figure 1 shows a 50 source resistor and a 2000pF capacitor to ground on the input will limit the input bandwidth to 1.6MHz. The source impedance has to be kept low to avoid gain error and degradation in the AC performance. The capacitor also acts as a charge reservoir for the input sample-and-hold and isolates the ADC input from sampling glitch sensitive circuitry. High quality capacitors and resistors should be
1000pF 50 DIFFERENTIAL ANALOG INPUTS CH0 1000pF 50 CH1 1000pF REFCOMP 10F
1863L7L F01b
W
UU
LTC1863L/ LTC1867L
Figure 1b. Optional RC Input Filtering for Differential Inputs
1863L7Lf
LTC1863L/LTC1867L
APPLICATIO S I FOR ATIO
used since these components can add distortion. NPO and silver mica type dielectric capacitors have excellent linearity. Carbon surface mount resistors can also generate distortion from self heating and from damage that may occur during soldering. Metal film surface mount resistors are much less susceptible to both problems. DC Performance One way of measuring the transition noise associated with a high resolution ADC is to use a technique where a DC signal is applied to the input of the ADC and the resulting output codes are collected over a large number of conversions. For example, in Figure 2 the distribution of output codes is shown for a DC input that had been digitized 4096 times. The distribution is Gaussian and the RMS code transition noise is about 1.6LSB.
1200 1044 1000 895 830 800 COUNTS 600 465 400 200 0 7 58 170 23 9 1 333 261 VDD = 2.7V INTERNAL REF
AMPLITUDE (dB)
20 21 22 23 24 25 26 27 28 29 30 31 CODE
1863L7L G12
AMPLITUDE (dB)
Figure 2. LTC1867L Histogram for 4096 Conversions
Dynamic Performance FFT (Fast Fourier Transform) test techniques are used to test the ADC's frequency response, distortion and noise at the rated throughput. By applying a low distortion sine wave and analyzing the digital output using an FFT algorithm, the ADC's spectral content can be examined for frequencies outside the fundamental. Signal-to-Noise Ratio The Signal-to-Noise and Distortion Ratio (SINAD) is the ratio between the RMS amplitude of the fundamental input frequency to the RMS amplitude of all other frequency
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components at the A/D output. The output is band limited to frequencies from above DC and below half the sampling frequency. Figure 3a shows a typical SINAD of 81.4dB with a 175kHz sampling rate and a 1kHz input. Higher SINAD can be obtained with a 3V supply. For example, when an external 3V is applied to REFCOMP (tie VREF to GND), a SINAD of 83.5dB can be achieved as shown in Figure 3b.
0 -20 -40 -60 -80 -100 -120 -140 0 21.875 43.75 65.625 FREQUENCY (kHz) 87.5 fSAMPLE = 175ksps fIN = 1kHz SNR = 82.9dB SINAD = 81.4dB THD = 86.8dB
1863L7L G03
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Figure 3a. LTC1867L Nonaveraged 4096 Point FFT Plot with 2.7V Supply
0 -20 -40 -60 -80 -100 -120 -140 0 21.875 43.75 65.625 FREQUENCY (kHz) 87.5 fSAMPLE = 175ksps fIN = 1kHz SNR = 84.7dB SINAD = 83.5dB THD = 90dB REFCOMP = EXT 3V
1863L7L F03b
Figure 3b. LTC1867L Nonaveraged 4096 Point FFT Plot with 3V Supply
Total Harmonic Distortion Total Harmonic Distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency
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LTC1863L/LTC1867L
APPLICATIO S I FOR ATIO
band between DC and half the sampling frequency. THD is expressed as:
THD = 20 log
V22 + V32 + V42 ... + VN2 V1
where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the second through Nth harmonics. Internal Reference The LTC1863L and LTC1867L have an on-chip, temperature compensated, curvature corrected, bandgap reference that is factory trimmed to 1.25V. It is internally connected to a reference amplifier and is available at VREF (Pin 10). A 3k resistor is in series with the output so that it can be easily overdriven by an external reference if better drift and/or accuracy are required as shown in Figure 4. The reference amplifier gains the VREF voltage by 2x to 2.5V at REFCOMP (Pin 9). This reference amplifier
R1 3k
1.25V
10 VREF 2.2F 9 REFCOMP REFERENCE AMP
BANDGAP REFERENCE
2.5V
10F
R2 R3 LTC1863L/LTC1867L
1863L7L F04a
15 GND
Figure 4a. LT1867L Reference Circuit
3V VIN LT1790A-1.25 VOUT 10 2.2F 9
SUPPLY CURRENT (A)
VREF LTC1863L/ LTC1867L REFCOMP
+
10F 0.1F 15
GND
1863L7L F04b
Figure 4b. Using the LT1790A-1.25 as an External Reference
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compensation pin, REFCOMP, must be bypassed with a 10F ceramic or tantalum in parallel with a 0.1F ceramic for best noise performance. Digital Interface The LTC1863L and LTC1867L have a very simple digital interface that is enabled by the control input, CS/CONV. A logic rising edge applied to the CS/CONV input will initiate a conversion. After the conversion, taking CS/CONV low will enable the serial port and the ADC will present digital data in two's complement format in bipolar mode or straight binary format in unipolar mode, through the SCK/ SDO serial port. Internal Clock The internal clock is factory trimmed to achieve a typical conversion time of 3.2s and a maximum conversion time, 3.7s, over the full operating temperature range. The typical acquisition time is 1.68s, and a throughput sampling rate of 175ksps is tested and guaranteed. Automatic Nap Mode The LTC1863L and LTC1867L go into automatic nap mode when CS/CONV is held high after the conversion is complete. With a typical operating current of 750A and automatic 170A nap mode between conversions, the power dissipation drops with reduced sample rate. The ADC only keeps the VREF and REFCOMP voltages active when the part is in the automatic nap mode. The slower the sample rate allows the power dissipation to be lower (see Figure 5).
800 700 600 500 400 300 200 100 1 10 100 fSAMPLE (ksps) 1000
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VDD = 2.7V
Figure 5. Supply Current vs fSAMPLE
1863L7Lf
LTC1863L/LTC1867L
APPLICATIO S I FOR ATIO
If the CS/CONV returns low during a bit decision, it can create a small error. For best performance ensure that the CS/CONV returns low either within 100ns after the conversion starts (i.e. before the first bit decision) or after the conversion ends. If CS/CONV is low when the conversion ends, the MSB bit will appear on SDO at the end of the conversion and the ADC will remain powered up. Sleep Mode If the SLP = 1 is selected in the input word, the ADC will enter SLEEP mode and draw only leakage current (provided that all the digital inputs stay at GND or VDD). After release from the SLEEP mode, the ADC needs 80ms to wake up (charge the 2.2F/10F bypass capacitors on VREF/REFCOMP pins). Board Layout and Bypassing To obtain the best performance, a printed circuit board with a ground plane is required. Layout for the printed circuit board should ensure digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital signal alongside an analog signal. All analog inputs should be screened by GND. VREF, REFCOMP and VDD should be bypassed to this ground plane as close to the pin as possible; the low impedance of
CS/CONV
tCONV
NAP MODE NOT NEEDED FOR LTC1863L 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
SCK
SDI Hi-Z
DON'T CARE
SD
SDO (LTC1863L) SDO (LTC1867L)
MSB D11 D10
Hi-Z
MSB D15 D14 D13 D12 D11 D10
Figure 6. Example 1, CS/CONV Starts a Conversion and Remains HIGH Until Next Data Transfer. With CS/CONV Remaining HIGH after the Conversion, Automatic Nap Modes Provides Power Reduction at Reduced Sample Rate
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the common return for these bypass capacitors is essential to the low noise operation of the ADC. The width for these tracks should be as wide as possible. Timing and Control Conversion start is controlled by the CS/CONV digital input. The rising edge transition of the CS/CONV will start a conversion. Once initiated, it cannot be restarted until the conversion is complete. Figures 6 and 7 show the timing diagrams for two types of CS/CONV pulses. Example 1 (Figure 6) shows the LTC1863L/LTC1867L operating in automatic nap mode with CS/CONV signal staying HIGH after the conversion. Automatic nap mode provides power reduction at reduced sample rate. The ADCs can also operate with the CS/CONV signal returning LOW before the conversion ends. In this mode (Example 2, Figure 7), the ADCs remain powered up. The digital output, SDO, will go HIGH immediately after the conversion is complete if the analog inputs are above half scale in unipolar mode or below half scale in bipolar mode. This is a way to measure the conversion time of the A/D converter. Figures 8 and 9 are the transfer characteristics for the bipolar and unipolar mode.
1/fSCK 0S S1 S0 COM UNI SLP DON'T CARE D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
1867 F06
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LTC1863L/LTC1867L
APPLICATIO S I FOR ATIO
CS/CONV
SCK
1
2
3
4
5
SDI
DON'T CARE t CONV
SD
0S
S1
S0
COM UNI
SDO (LTC1863L) SDO (LTC1867L)
MSB = D11 Hi-Z t CONV MSB = D15 Hi-Z
D10
D9
D8
D7
D6
D14 D13 D12 D11 D10
Figure 7. Example 2, CS/CONV Starts a Conversion with Short Active HIGH Pulse. With CS/CONV Returning LOW Before the Conversion, the ADC Remains Powered Up.
OUTPUT CODE (TWO'S COMPLEMENT)
011...111 011...110 BIPOLAR ZERO
OUTPUT CODE
000...001 000...000 111...111 111...110 FS = 2.5V 1LSB = FS/2n 1LSB (LTC1863L) = 610V 1LSB (LTC1867L) = 38.1V -FS/2 -1 0V 1 LSB LSB INPUT VOLTAGE (V) FS/2 - 1LSB
1863L7L F08
100...001 100...000
Figure 8. LTC1863L/LTC1867L Bipolar Transfer Characteristics (Two's Complement)
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tACQ NOT NEEDED FOR LTC1863L 6 7 8 9 10 11 12 13 14 15 16 SLP DON'T CARE D5 D4 D3 D2 D1 D0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
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111...111 111...110
100...001 100...000 011...111 UNIPOLAR ZERO 011...110 FS = 2.5V 1LSB = FS/2n 1LSB (LTC1863L) = 610V 1LSB (LTC1867L) = 38.1V 0V INPUT VOLTAGE (V)
1863L7L F09
000...001 000...000
FS - 1LSB
Figure 9. LTC1863L/LTC1867L Unipolar Transfer Characteristics (Straight Binary)
1863L7Lf
LTC1863L/LTC1867L
PACKAGE DESCRIPTIO U
GN Package 16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.045 .005
.189 - .196* (4.801 - 4.978) 16 15 14 13 12 11 10 9
.009 (0.229) REF
.254 MIN
.150 - .165
.229 - .244 (5.817 - 6.198)
.150 - .157** (3.810 - 3.988)
.0165 .0015
.0250 BSC
RECOMMENDED SOLDER PAD LAYOUT
1
23
4
56
7
8
.004 - .0098 (0.102 - 0.249)
.015 .004 x 45 (0.38 0.10)
.007 - .0098 (0.178 - 0.249) 0 - 8 TYP
.0532 - .0688 (1.35 - 1.75)
.016 - .050 (0.406 - 1.270)
NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) 3. DRAWING NOT TO SCALE *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
.008 - .012 (0.203 - 0.305) TYP
.0250 (0.635) BSC
GN16 (SSOP) 0204
1863L7Lf
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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LTC1863L/LTC1867L
RELATED PARTS
PART NUMBER LTC1417 LT1468/LT1469 LTC1609 LT1790 LT1790A-1.25 LTC1850/LTC1851 LTC1852/LTC1853 LTC1860/LTC1861 LTC1860L/LTC1861L LTC1863/LTC1867 LTC1864/LTC1865 LTC1864L/LTC1865L DESCRIPTION 14-Bit, 400ksps Serial ADC Single/Dual 90MHz, 22V/s, 16-Bit Accurate Op Amps 16-Bit, 200ksps Serial ADC Micropower Low Dropout Reference Micropower Precision Series Reference 10-Bit/12-Bit, 8-Channel, 1.25Msps ADC 10-Bit/12-Bit, 8-Channel, 400ksps ADC 12-Bit, 1-/2-Channel 250ksps ADC in MSOP 3V, 12-Bit, 1-/2-Channel 150ksps ADC 12-/16-Bit, 8-Channel 200ksps ADC 16-Bit, 1-/2-Channel 250ksps ADC in MSOP 3V, 16-Bit, 1-/2-Channel 150ksps ADC in MSOP COMMENTS 20mW, Unipolar or Bipolar, Internal Reference, SSOP-16 Package Low Input Offset: 75V/125V 65mW, Configurable Bipolar and Unipolar Input Ranges, 5V Supply 60A Supply Current, 10ppm/C, SOT-23 Package Bandgap, 60A Max Supply Current, 10ppm/C, SOT-23 Package Parallel Output, Programmable MUX and Sequencer, 5V Supply Parallel Output, Programmable MUX and Sequencer, 3V or 5V Supply 850A at 250ksps, 2A at 1ksps, SO-8 and MSOP Packages 450A at 150ksps, 10A at 1ksps, SO-8 and MSOP Packages 5V Supply, Pin Compatible with LTC1863L/LTC1867L 850A at 250ksps, 2A at 1ksps, SO-8 and MSOP Packages 450A at 150ksps, 10A at 1ksps, SO-8 and MSOP Packages
1863L7Lf
16
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 FAX: (408) 434-0507
LT/TP 0105 1K * PRINTED IN USA
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2005

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